Index of /MCU/Frameworks/ARM/stm32f1

 Name                    Size  

 Parent Directory            -  
 Makefile                   1k  
 cpu.c                      1k  
 cpu.h                      1k  
 gpiopins.c                 1k  
 gpiopins.h                19k  
 leds.c                     2k  
 libs/                       -  
 serial.c                   7k  
 spi.c                      9k  
 stm32f1.flashocd           1k  
 stm32f1.mk                 1k  
 stm32f100rb.S              6k  
 stm32f100rb.debugjlink     1k  
 stm32f100rb.eprj           2k  
 stm32f100rb.ld             1k  
 stm32f100rb.mk             1k  
 stm32f100rb.openocd        1k  
 stm32f103c8.S              6k  
 stm32f103c8.debugjlink     1k  
 stm32f103c8.eprj           2k  
 stm32f103c8.ld             1k  
 stm32f103c8.mk             1k  
 stm32f103c8.openocd        1k  
 stm32f103rb.S              6k  
 stm32f103rb.debugjlink     1k  
 stm32f103rb.eprj           2k  
 stm32f103rb.ld             2k  
 stm32f103rb.mk             1k  
 stm32f103rb.openocd        1k  
 stm32f107rb.S              6k  
 stm32f107rb.debugjlink     1k  
 stm32f107rb.eprj           2k  
 stm32f107rb.ld             2k  
 stm32f107rb.mk             1k  
 stm32f107rb.openocd        1k  
 test_conio.c               2k  
 test_float.c               1k  
 test_freertos.c            3k  
 test_gpio.c                2k  
 test_spi.c                 2k  
 test_systick.c             1k  
 test_wiznet.c              7k

ST STM32F1 Cortex-M3 ARM Microcontroller Framework

Credits

The C run time startup code stm32f1xxxx.S and linker script stm32f1xxxx.ld were written by myself based on various examples on the Internet and in The Definitive Guide to the ARM Cortex-M3.

Other files are original works by myself, and are hereby placed into the public domain.

Memory Map (STM32F107RB)

Code Flash:	`0x00000000 to 0x0003FFFF`	256 KB
Data RAM:	`0x20000000 to 0x2000FFFF`	64 KB

The STM32F1 microcontrollers can have any of code flash at 0x08000000, system memory (serial boot loader) at 0x1FFFF000, or data ram at 0x20000000 mapped to address 0x00000000, depending on the BOOT0 and BOOT1 pins. This framework assumes BOOT0 is strapped low, mapping code flash to 0x00000000.

This framework assumes a single stack for both thread and handler modes, using MSP (Main Stack Pointer) at the top of RAM. The C heap is placed at the end of BSS data.

Other Devices

This framework may be used for other devices in the ST STM32F1 family, provided the following files are modified:

`stm32f1xxxx.ld`	The RAM and ROM sizes must match the device.
`cpu.h`	The default CPU frequency must match the device.
`cpu.c`	The clock initialization code must match the device.

Test Platform

This framework is validated on the Olimex STM32-P103, Olimex STM32-P107, and STM32 Value Line Discovery development boards.

Tested on 30 November 2011 with gcc 4.6.2.

Questions or comments to Philip Munts phil@munts.net

$Id: README.html 3506 2011-12-02 12:10:23Z svn $

I am available for custom system development (hardware and software) of products using the STM32F1 or other microcontrollers.